To reduce the time and investment required for design, debugging, and enhancement, designs may be implemented using programmable integrated circuits (IC). Programmable ICs include a number of logic and routing resources that may be configured to implement a circuit design. Programmable ICs allow a circuit design to be implemented, tested, and revised without realizing the circuit design as an application specific IC (ASIC). In this manner, development time and costs may be reduced.
Many applications, such as high-speed networking applications, require a significant amount of memory (e.g., DRAM) to buffer data for processing. However, such large amounts of memory are generally not available on programmable ICs. To satisfy the memory requirements of the application, several memory blocks may be implemented on a separate IC and a memory controller implemented on the programmable IC to communicate data between logic circuitry of the programmable IC and the external memory over a parallel data bus. However, throughput in this type of memory arrangement may be limited by memory specific timing constraints. Furthermore, many parallel interfaces have to be implemented in order to achieve the required access bandwidth. Ultimately, there are often not enough I/O pins available in a programmable IC package to provide sufficient off-chip bandwidth to external memory.
More recent memory architectures, known as hybrid memory cubes, overcome the input/output (I/O) bottleneck by integrating a memory controller on the same external chip as the memory and providing access through read and write commands packetized on high-speed serial data links. These high-speed serial links offer significantly more off-chip bandwidth than the standard I/Os that are used for the traditional memory interfaces. Furthermore, by offloading the memory controller from the programmable IC, additional resources are freed.